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Cmos Lna Design Techniques

IEEE 2006 Custom Intergrated Circuits Conference (CICC)

X/Ku Band CMOS LNA Design Techniques
Bagher Afshar, Ali M. Niknejad Berkeley Wireless Research Center, Dept. of EECS, UC Berkeley, Berkeley, CA 94704, USA

Abstract— This paper reports two 11 GHz low-noise amplifiers (LNA) in 0.18µm CMOS technology. A cascade two stage LNA achieves 12 dB of power gain, 3.5 dB of noise figure, and an input/output match of −15 dB/−27 dB at 11GHz, while consuming 28mA from 1.8V supply. The second LNA is a modified cascode amplifier and it achieves 8 dB of gain, 3.1 dB of noise figure, and an input/output match of −12 dB/−15 dB at 11GHz, consuming 18mA from the 1.8V supply. The paper also discusses design considerations such the effects of layout on frequency tuning and noise.

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I. I NTRODUCTION Rapid evolution of wireless communication has resulted in a continuous trend towards utilizing higher frequencies for wideband communication applications. CMOS technology is of major interest for its low cost and high level of integration. While much research has been done on integrating cellular and WLAN transceivers in CMOS and SiGe technology [1], very little work has been done at 10GHz (X-band, Ku-band). There are many interesting and important commercial applications in this frequency band, such as the satellite communication receivers for entertainment and high speed internet access. Current microwave receivers at this frequency are not only physically large, but are also expensive. Realization of such devices in standard CMOS will enable wider commercial adoption. On the other hand much research activity has recently focused on higher frequencies, such as the 60GHz band [2] and the 77GHz band [3]. Unfortunately microwave transmission-line based design techniques do not scale to relatively lower frequencies like 10GHz. Due to area constrains, circuits at these frequencies must employ relatively...